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Computer Organization & Architecture
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Course Name
BCA (Bachelor of Computer Application)
Subject Code BC0040 (Computer Organization & Architecture)
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PART - A
PART - B
PART - C
Computer Organization & Architecture Syllabus.
Unit 1 Basic Structure of a Digital Computer
Introduction , Structure of a computer system , Central processing Unit ,
Memory Unit , Input/Output , System interconnection , Arithmetic Logic Unit
,Control Unit , Bus Structure , Von Neumann Architecture
Unit 2 CPU and Register Organization
Register Organization , User-visible Registers , Control and Status
Registers , Program Status Word (PSW) , CPU Organization , Study of CPU
organization in 8085 microprocessor , Example of Register Organization in
different machine , The Zilog Z8000 machine , Intel 8086 machine , Motorola
68000 machine , Instruction cycle , Basic instruction cycle , Basic instruction
state diagram
Unit 3 Interconnection Structures
Types of exchange of information , Modules of System , Different types of
transfers , Types of Buses , Elements of Bus Design , Bus Types , Method of
arbitration , Bus Timing , Bus width , Bus Structure , Single Bus System , Two
Bus Organization , The Bus Standard
Unit 4 Instruction sets: Addressing Methods and formats
Introduction , instruction Characteristics Instruction representation ,
Instruction types , Number of addresses , Instruction Set Design , Types of
Operands , Data types , IBM 370 Data types , VAX Data types , Types of
Operations , Data transfer , Arithmetic , Logical , Conversion , I/O, system
control , Transfer of control , System Control, Addressing Modes , Direct
addressing mode , Immediate addressing mode , Indirect addressing mode ,
Register addressing mode , Register Indirect addressing mode , Displacement
addressing mode , Relative addressing mode, Base address addressing , Indexing ,
Stack addressing , Other additional addressing , Instruction formats ,
Instruction Length , Allocation of bits , Variable length instruction , Stacks &
Subroutines , Stacks ,Subroutines
Unit 5 ALU and Binary Arithmetic
Introduction, Arithmetic Logic Unit, Number Representations, Binary
Arithmetic, Floating point Number, Real Numbers
Unit 6 Memory Unit
Introduction, Characteristics of Memory Systems, Main Memory , Types of
Random- Access Semiconductor Memory , Organization , Static and dynamic memories
,Memory system considerations ,Design of memory subsystem using Static Memory
Chips , Design of memory subsystem using Dynamic Memory Chips ,Memory
interleaving , Cache Memory , Principles of cache memory , Structure of cache
memory, Performance using cache memory , Elements of Cache Design , Mapping
functions , Replacement algorithms , External Memory , Magnetic Disk , RAID ,
Virtual memory , Memory Management in Operating Systems
Unit 7 Input/Output
Introduction , External Devices , Classification of external devices ,
Input/Output problems , Input/Output Module , I/O Module Function , I/O Module
Decisions , Input Output Techniques , Programmed I/O , I/O commands , I/O
instructions , Interrupt Driven I/O , Basic concepts of an Interrupt , Response
of CPU to an Interrupt , Design Issues , Priorities , Interrupt handling , Types
of Interrupts , Direct Memory Access , DMA Function and Operation , DMA
Configurations , DMA Controller , DMA Transfer Types , DMA Transfer modes , DMA
Controller Operation , Advantages , Synchronization Requirements for DMA and
Interrupts , Synchronization with Interrupts , Synchronization with DMA
Unit 8 Control Unit
Fundamental concepts , Micro operations , Micro operations of Fetch cycle ,
Indirect Cycle , The execute cycle , The Instruction cycle , Control of the CPU
, Functional Requirements , Control Signals , Data paths and control signals ,
Data Path Inside A CPU , Single bus structure , Two bus structure , Three bus
structure , Execution of a complete instruction , Branching , Sequencing Of
Control Signals , Hardwired Control Unit , Micro-Programmed Control
Unit 9 Parallel Model of Computers and Pipelining
Introduction , Parallel/Vector Computers , Parallelism and pipelining ,
Classification based on data streams and instructions , Parallel/Vector
Computers , Development Layers , New
Challenges , Pipelining , Principles of Linear Pipelining , Pipeline structure
of CPU , Timings of pipelining, Effect of pipelining , Basic Performance Issues
in Pipelining , The
Major Hurdle of Pipelining , Structural Hazards , Data Hazards , Control Hazards
Unit 10 Advanced Processor Technology
Introduction , Instruction set Architecture , RISC and CISC ,
Characteristics of CISC ,
Characteristics of RISC , RISC versus CISC , Instruction set complexity- RISC
versus CISC , Vector processing requirements , Characteristics of vector
processing , Multiple vector task dispatching , Super scalar processors , The
emergence and spread of super scalar processors , Specific task of Super scalar
processing , Super Scalar instruction issue , The design space , Issue policies
, Instruction issue policies of scalar processors , Instruction issue policies
of superscalar processors
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