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Computer Architecture
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Course Name
MSc IT (Master of Science in Information Technology)
Subject Code MT0041 (Computer Architecture)
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PART - A
PART - B
PART - C
Subject : Computer Architecture
MT0041 : PART - A
| Q. 1 | After performing an execution by A.L.U the information is stored in ____ |
| | A) | Accumulator |
| B) | Control unit | | C) | Secondary memory | | D) | None of the above | | | | | Q. 2 | ____ is a logical instruction |
| | A) | MOV |
| B) | CMP | | C) | LDA | | D) | None | | | | | Q. 3 | Set of all instructions for a specific function is called : ____ |
| | A) | Operands set |
| B) | Instruction set | | C) | Module set | | D) | None of the above | | | | | Q. 4 | A digital circuit that generates the arithmetic sum of two binary number s of any length is ______ |
| | A) | Binary adder |
| B) | Decimal adder | | C) | Hexa-decimal adder | | D) | None | | | | | Q. 5 | ____ is used to store the address of the next instruction to be executed |
| | A) | I.R |
| B) | A.L.U | | C) | Accumulator | | D) | Program counter | | | | | Q. 6 | The program controller and A.L.U together form a ___ |
| | A) | Main memory |
| B) | C.P.U | | C) | Auxiliary memory | | D) | None of the above | | | | | Q. 7 | ____ is a data transfer instruction |
| | A) | MOV |
| B) | LDA | | C) | HLT | | D) | Both a & b | | | | | Q. 8 | ____ mode of addressing the operands are n registers that reside with in C.P.U. |
| | A) | Register mode |
| B) | Intermediate mode | | C) | Direct mode | | D) | Both a & b | | | | | Q. 9 | The C.P.U consists small storage devices called _____ |
| | A) | Register |
| B) | Flip-flops | | C) | Accumulator | | D) | All the above | | | | | Q. 10 | A ____ is capable to store single binary bit |
| | A) | Capacitor |
| B) | Flip-flop | | C) | Register | | D) | Inductor | | | |
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