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# Digital Systems, Computer Organization & Architecture

This is the collection of Sikkim Manipal University (SMU) question and answers for Digital Systems, Computer Organization & Architecture. It will help to prepare your examination. All question paper are classified as per semester, subject code and question type of Part A, Part B and Part C with multiple choice options as same as actual examination. SMU question papers includes year 2019, 2018, 2017 Sem I, II, III, IV, V, VI examinations of all subjects.

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Course Name        MCA (Master of Computer Application)

Subject Code       MC0062 (Digital Systems, Computer Organization & Architecture)

Get Questions        PART - A    PART - B    PART - C

Digital Systems, Computer Organization & Architecture Syllabus.

Part 1: Number Systems
The Decimal Number System; The Binary Numbering System: Counting in Binary, Binary to Decimal Conversion, Decimal to Binary Conversion: Sum of Weight Method, Repeated Division Method, Repeated Multiplication;The Octal Numbering System: Counting in Octal, Octal to Decimal Conversion, Decimal to Octal Conversion, Sum of Weight Method, Repeated Division Method, Repeated Multiplication, Octal to Binary Conversion, Binary to Octal Conversion; The Hexadecimal Numbering System: Hexadecimal to Binary Conversion, Binary to Hexadecimal Conversion, Hexadecimal to Decimal Conversion, Hexadecimal to Octal Conversion, Decimal to Octal Conversion, Sum of Weight Method, Repeated Division Method, Repeated Multiplication; Binary Arithmetic: Binary Addition, Binary Subtraction, Binary Multiplication, Binary Division, Complementary numbering systems, 1‘s and 2‘s Complements, Binary subtraction using 1‘s complementary Method, Binary subtraction using 2‘s complementary Method; Binary Coded Decimal (BCD) Numbering system: BCD Addition.

Part 2: Boolean Algebra
Addition and Multiplication in Boolean algebra; Binary Logic Functions, Logical Gates and Truth Tables: NOT Logic, AND Logic, OR Logic, NAND Logic, NOR Logic, Ex – OR Logic, Ex – NOR Logic; Boolean Rules and Laws: Commutative law, Associative Law, Distributive Law, Boolean Rules; DEMORGAN‘s Theorem.

Part 3: Combinational Logic
Realization of switching functions using logic gates; Canonical Logic Forms: Sum of Products Form, Product of Sum Form; Universal Gate: NAND Gate as Universal Gate, NOR Gate as Universal Gate, Realization of Boolean Functions using Universal Gates; Timing Diagrams and Synchronous Logic; Realization of Combinational circuits from the truth table.

Part 4: Combination logic realization
Karnaugh Map or K – Map; Plotting a Boolean expression; Logic expression simplification with grouping cells; Quine McClusky Method: Prime implicants, Prime implicant chart.

Part 5: Analysis and Design of Combinational Logic
Binary adders: Half adder; Full adder; Binary Subtractor: Half subtractor, Full subtractor; Parallel Binary Adders; BCD Adders; Binary Comparator or Magnitude Comparator; Decoders: Basic Binary Decoder, 3 line to 8 line Decoder; Encoders: Decimal to BCD encoder, Octal to Binary Encoder; Priority Encoder: Decimal to BCD priority encoder; Code conversion: BCD to Binary conversion, Gray Code, Binary to Gray Conversion, Gray code to Binary Conversion; Multiplexers or Data Selectors; Multiplexers as logic function generators; Demultiplexers; Parity Generators and Parity Checkers: Parity, Detecting an Error.

Part 6: Latches and Flip Flops
Latches: The S-R Latch: Active HIGH S-R Latch (NOR gate S-R Latch), Active Low S-R Latch ( NAND Gate S-R Latch); Gated Latches: Gated S-R Latches, Gated D-Latch or D-flip-flop; Edge triggered Flip-Flops: Edge triggered S-R Flip-Flop (S-R FF), Edge triggered D-Flip-Flop (D-FF), Edge triggered J-K Flip-Flop (J-K FF); Asynchronous inputs: PRESET and CLEAR; Master-Slave J-K Flip Flop.

Part 7: Asynchronous Counters
Asynchronous Counters: Negative edge triggered 2-bit ripple Up-counter, Negative edge triggered 2-bit ripple Down-counter, Negative edge triggered 2-bit ripple up/down-counter; Design of modulus counters; Cascading of Ripple Counter; Integrated Circuit Asynchronous Ripple Counter: IC 7493 – A 4-bit Binary Counter, IC 7490 – A Decade Counter.

Part 8: Synchronous Counters
Up- Counters: Two bit Synchronous Binary Counters, A Three-bit Synchronous Binary Up-counter, A Four-bit Synchronous Binary Up-counter, Synchronous Decade Up-counter; Down- Counters: Two bit Synchronous Binary Counters, A Three-bit Synchronous Binary down-counter, A Four-bit Synchronous Binary down-counter.

Part 9: Shift Registers
Shift Register Classification; Serial-in, Serial-out shift register: Timings in Serial Shift operation, Serial In, Serial out Shift operation – 3 register combination; Serial In, Parallel out Shift Register; Parallel In, Parallel out Shift Register; 74LS395 – A Universal Shift Register: Serial in, Serial Out Right Shift Operation of 74LS395, Serial in, Serial Out Left Shift Operation of 74LS395; Ring counters; Johnson counters.

Part 10: Data Converters
Digital to Analog Converters (DAC): Binary Weighted Input Method, The R-2R Ladder DAC; Analog to Digital Converters (ADC): Flash Type ADC, Staircase Ramp or Digital Ramp Type; Slope Integrator Type: Single Slope Integrator Type, Dual Slope Integrator Type; Successive Approximation Method; Practical Considerations of ADCs: Resolution, Conversion Rate or Sample Frequency, Step Recovery. Book 2: Computer Organization & Architecture

Part 1: Basic Structure of a Digital Computer
Mechanical and Electromechanical ancestors; Structure of a computer system: Central processing Unit, Memory Unit, Input/Output and I/O Interface, System interconnection; Arithmetic Logic Unit; Control Unit; Bus Structure; Von Neumann Architecture.

Part 2: CPU and Register Organization
Introduction: User-visible Registers, Control and Status Registers, Program Status Word (PSW); CPU Organization: Fundamental Computer Architecture, CPU organization in 8085 microprocessor; Register Organization of different machine: The Zilog Z8000 machine, Intel 8086 machine, Motorola 68000 machine; Instruction cycles: Basic instruction cycle, Basic instruction Cycle state diagram.

Part 3: Interconnection Structures
Types of exchange of information: Modules of a System, Different types of transfers; Types of Buses ; Elements of Bus Design: Bus Types, Method of arbitration, Bus Timing, Bus width, Bus Speed; Bus Structure: Single Bus System, Two Bus Organization, The Bus Standard.

Part 4: Instruction sets: Addressing Modes and formats

Part 5: ALU and Binary
Arithmetic: Arithmetic Logic Unit; Number Representations: Non-negative Integers, Negative Integers, Infinite-Precision Ten's Complement, Finite-Precision Ten's Complement, Finite-Precision Two's Complement, Rational Numbers; Binary Arithmetic: Overflow in Integer Arithmetic, Binary Addition, Subtraction, Another Note on Overflow, Multiplication, Unsigned Integer Multiplication: Straightforward Method, Unsigned Integer Multiplication: A More Efficient Method, Positive Integer Multiplication, Signed Integer Multiplication, Division; Floating Point Numbers: Floating Point Variables, Floating Point Arithmetic, Addition of Floating-Point Numbers, Time for Floating-Point Addition, Pipelined Floating-Point Addition; Real Numbers.

Part 6: Memory Unit
Characteristics of Memory Systems; Main Memory: Types of Random-Access Semiconductor Memory, Organization, Static and dynamic memories; Memory system considerations: Design of memory subsystem using Static Memory Chips, Design of memory subsystem using Dynamic Memory Chips; Memory interleaving; Cache Memory: Principles of cache memory, Structure of cache and main memory, Performance using cache memory, Elements of Cache Design, Mapping functions, Replacement algorithms; External Memory: Magnetic Disk, RAID; Virtual memory; Memory Management in Operating Systems.

Part 7: Input/Output
External Devices: Classification of external devices, Input/Output problems; Input/Output Module: I/O Module Function, I/O Module Decisions, Input Output Techniques, Programmed I/O: I/O commands, I/O instructions; Interrupt Driven I/O: Basic concepts of an Interrupt, Response of CPU to an Interrupt, Design Issues, Priorities, Interrupt handling, Types of Interrupts; Direct Memory Access: DMA Function and Operation, DMA Configurations; DMA Controller: DMA Transfer Types, DMA Transfer modes, DMA Controller Operation, Advantages; Synchronization Requirements for DMA and Interrupts: Synchronization with Interrupts, Synchronization with DMA.

Part 8: Control Unit
Micro operations: Micro operations of Fetch cycle, Indirect Cycle, The execute cycle, The Instruction cycle; Control of the CPU: Functional Requirements, Control Signals, Data paths and control signals; Data Path inside A CPU: Single bus structure, Two bus structure, Three bus structure, Execution of a complete instruction, Branching; Sequencing of Control Signals: Hardwired Control Unit, Micro-Programmed Control.

Part 9: Parallel Model of Computers and Pipelining
Introduction: Lookahead, Parallelism and pipelining, Flynn‘s Classification; Parallel/Vector Computers: Development Layers, New Challenges; Pipelining: Principles of Linear Pipelining, Pipeline structure of CPU, Timings of pipelining, Effect of pipelining; Basic Performance Issues in Pipelining; The Major Hurdle of Pipelining: Structural Hazards,Data Hazards, Control Hazards.

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