Course Name
BSc IT (Bachelor of Science in Information Technology)
Subject Code BT0068 (Computer Organization and Architecture )
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PART  A
PART  B
PART  C
Computer Organization and Architecture Syllabus.
Unit 1: Data Representation in Computers
Digital Computers; Data Types; Complements; FixedPoint Representation;
FloatingPoint Representation; Other Binary Codes;
Unit 2: Register
Transfer and Micro operations Register Transfer Language; Register Transfer;
Bus and Memory Transfers; Arithmetic Microoperations; Logic Microoperations;
Shift Microoperations; Arithmetic Logic Shift Unit.
Unit 3: Basic Structure of a Digital Computer
Mechanical and Electromechanical Ancestors; Structure of a Computer System;
Arithmetic Logic Unit; Control Unit; Bus Structure; on Neumann Architecture.
Unit 4: CPU and Register
Organization Registers; UserVisible Registers; Control and Status
Registers; Program Status Word (PSW); CPU Organization; Fundamental Computer
Architecture; CPU organization in 8085 microprocessor. Register Organization of
different machine; The Zilog Z8000 machine; Intel 8086 machine; Motorola 68000
machine. Instruction cycles; Basic instruction cycle; Basic instruction Cycle
state diagram.
Unit 5: Interconnection Structures
Types of exchange of information: Modules of a System, Different types of
transfers; Types of Buses; Elements of Bus Design: Bus Types, Method of
arbitration, Bus Timing, Bus width; Bus Speed; Bus Structure: Single Bus System,
Two Bus Organization, The Bus Standard.
Unit 6: Instruction Sets;
Addressing Modes and Formats Instruction Characteristics: Instruction
representation, Instruction types, Number of addresses; Instruction Set Design;
Types of Operands: Data types, IBM 370 Data types, VAX Data types; Types of
Operations: Data transfer, Arithmetic, Logical, Conversion; I/O, System control;
Transfer of control, System Control ;Addressing Modes: Direct addressing mode,
Immediate addressing mode, Indirect addressing mode, Register addressing mode,
Register indirect addressing mode, Displacement addressing mode, Relative
addressing mode.
Unit 7: Arithmetic Logic Unit
Arithmetic Logic Unit; Number Representations: Onnegative Integers,
Negative Integers; InfinitePrecision Ten's Complement, FinitePrecision Ten's
Complement, FinitePrecision Two's Complement, Rational Numbers.
Unit 8: Binary Arithmetic
Binary Arithmetic: Overflow in Integer Arithmetic, Binary Addition,
Subtraction, another Note on Overflow, Multiplication, Unsigned Integer
Multiplication, Straightforward Method, Unsigned Integer Multiplication, A More
Efficient Method, Positive Integer Multiplication; Signed Integer
Multiplication, Division; Floating Point Numbers: Floating Point Variables,
Floating Point Arithmetic, Addition of FloatingPoint Numbers, Time for
FloatingPoint Addition, Pipelined FloatingPoint Addition, Real Numbers.
Unit 9: Memory Unit – Part I
Characteristics of Memory Systems, Main Memory, Types of RandomAccess
Semiconductor Memory, Organization, Static and dynamic memories; Memory system
considerations, Design of memory subsystem using Static Memory Chips, Design of
memory subsystem using Dynamic Memory Chips; Memory interleaving.
Unit 10: Memory Unit – Part II
Cache Memory: Principles of cache memory, Structure of cache and main
memory, Performance using cache memory, Elements of Cache Design. Mapping
functions, Replacement algorithms; External Memory, Magnetic Disk, RAID; Virtual
memory; Memory Management in Operating Systems.
Unit 11: Input / Output
Basics External Devices: Classification of external devices, Input / Output
problems; Input / Output Module: I/O Module Function, I/O Module Decisions,
Input Output Techniques; Programmed I/O:I/O commands, I/O instructions;
Interrupt Driven I/O:Basic concepts of an Interrupt, Response of CPU to an
Interrupt, Design Issues, Priorities,Interrupt handling, Types of Interrupts.
Unit 12: Direct Memory Access
Direct Memory Access: DMA Function and Operation, DMA Configurations; DMA
Controller: DMA Transfer Types, DMA Transfer modes, DMA Controller Operation,
Advantages. Synchronization Requirements for DMA and Interrupts: Synchronization
with Interrupts, Synchronization with DMA.
