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Computer Organization and Architecture
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Course Name
BSc IT (Bachelor of Science in Information Technology)
Subject Code BT0068 (Computer Organization and Architecture )
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PART - A
PART - B
PART - C
Subject : Computer Organization and Architecture
BT0068 : PART - A
| Q. 1 | ____ mode of addressing the operands are n registers that reside with in C.P.U. |
| | A) | Register mode |
| B) | Intermediate mode | | C) | Direct mode | | D) | Both a & b | | | | | Q. 2 | The clock pulses are generated by ____ component of control unit |
| | A) | Clock chip |
| B) | Accumulator | | C) | Clock cycle | | D) | Controller | | | | | Q. 3 | The time interval to position the location of a data element in the memory is ____ |
| | A) | Fetch cycle |
| B) | Instruction cycle | | C) | Execution cycle | | D) | Memory cycle | | | | | Q. 4 | An ____ incorporates a complete transistor circuit into a tiny chip of semi conductor material. |
| | A) | I.C |
| B) | L.S.I | | C) | V.L.S.I | | D) | All of the above | | | | | Q. 5 | The sum of memory cycle & fetch cycle is called _____ |
| | A) | Instruction cycle |
| B) | Operation cycle | | C) | Control cycle | | D) | Execution cycle | | | | | Q. 6 | ____ are used in digital computers for simplify the subtraction operations |
| | A) | Shift left |
| B) | Complements | | C) | Shift right | | D) | None of the above | | | | | Q. 7 | The result generated by A.L.U is received by internal main memory from ____ |
| | A) | Secondary memory |
| B) | Hard disk | | C) | Accumulator | | D) | None of the above | | | | | Q. 8 | ____ component is used to compare the magnitudes of the two numbers. |
| | A) | Comparator |
| B) | Inductor | | C) | Capacitor | | D) | Adder | | | | | Q. 9 | ____ is a data transfer instruction |
| | A) | MOV |
| B) | LDA | | C) | HLT | | D) | Both a & b | | | | | Q. 10 | An __ is a command to the micro processor to perform a given task on specified data |
| | A) | Instruction |
| B) | Program | | C) | Syntax | | D) | None | | | |
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